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Faster Than the Speed of Light
By William D. Kimmel, P.E.
and Daryl D. Gerke, P.E.
As switching speeds get faster, we find EMI problems and
Signal Integrity problems merge into one common problem, generally
starting and ending at the chip. In both cases, fast risetimes
are the key issue. While they allow faster operations, they
create lots of signal integrity and EMI problems in the process.
The Bay Area gurus are competing with each other to become
the first to build a switch with zero risetime. We don’t
believe they will get there, anymore than they will get the
signals to go faster than the speed of light (hence, the title
of this article), but it won’t be for lack of trying.
Let’s take a look at the issue, and where it might be
heading.
The Problem
The problem is the speed of light. While the general public
considers the speed of light to be very fast indeed, we electronics
people run up against the speed limitations on a regular basis.
While light may travel 186,000 miles in a second, it only
travels about a foot in one nS in air and about half that
distance in a typical dielectric.
At this time, microprocessor clock speeds are nudging 4Ghz,
which translates to a period of about 250pS and a clock pulse
width of about 125pS. Risetimes will necessarily be well below
100pS. In a dielectric media, light travels less than one
inch in this time. Noting that transmission line behavior
becomes significant when the round trip propagation delay
is comparable with the rise time (L in inches > 3*tr in
nS) which, for a 4Ghz clock, is a path length of less than
0.1 inch. Longer than that, impedance control is necessary.
For practical purposes, this means that any signal that leaves
the die needs to be impedance controlled, and the termination
needs to be on the die. That creates a problem that has not
been solved – while the principle is straightforward,
the practice is cumbersome, at best. This is why you don’t
see GHz signals leaving and entering the chip. Generally,
bus rates are no more than about 200MHz. What do we do about
those?
Impedance Control from Tip to Tip
One aspect of impedance control is that the entire signal
path geometry needs to be controlled. The textbooks have an
easy solution, a simple path from driver to receiver. When
we are talking about cables, the geometry is uniform along
the way, so the only impedance uncertainty is at the ends,
and control is fairly easy. But on-board, we usually don’t
have a nice homogenous path along the way – we will find
the signal path bending around corners, passing through vias.
Figure 1 shows two of the worst cases, one where the signal
switches reference planes along the way and the other where
the signal crosses a slot in the plane. Here is a list of
discontinuities we run into regularly:
Signal Vias. This is where the signal drops through a via.
The problem is minimal where the signal continues on the other
side of the same reference plane, much worse if the signal
switches from a ground plane to a voltage plane in the process.
The best solution is to keep the signal on one layer from
source to load. If you need to go through a via to change
directions, you have a minimal discontinuity if you stay with
the same plane. Keep the hole as small as you can.
If you need to switch reference planes, your best bet is to
go from ground to ground. In such a case, you can minimize
the discontinuity by dropping a ground to ground via alongside
the signal via. Better yet, drop four ground-to-ground vias
around the perimeter of the signal via to simulate a short
coax.
If you have to switch from a ground to a voltage reference
plane, you will have a significant discontinuity no matter
what you do. Your only choice is to run a decoupling path
from power to ground immediately alongside the signal via.
This is decidedly a compromise solution, but is better than
nothing. The argument that the interlayer capacitance provides
the return path is open to question. At the higher frequencies
(say, above 500MHz), the interlayer capacitance is starting
to become a significant factor, validating the argument. At
lower frequencies, the capacitance is too diffuse to solve
the problem, so a decap is necessary.
We expect to see this problem reduced with the new high-K
dielectrics, providing significantly more local capacitance.
Slotted or Split Planes. This is there the signal crosses
a slot in the plane, either because the PCB designer borrowed
some copper to accommodate another trace, or because there
is a necessary split in the voltage plane to accommodate several
supply voltages. This situation also occurs at connectors
where the copper has been cut away. The answer is simple:
avoid doing this. If you absolutely must cross a split plane
boundary (as in changing supply voltages from 3.3 to 1.8,
for example), then your only option is to bridge the planes
with a decap immediately adjacent to the signal lines, preferably
on both sides of the trace.
Signal Return on Chip. This is where the signal leaves the
chip via a signal pin and returns through a ground (or perhaps
voltage) pin. You have no choice in this matter – the
vendor has defined the pinouts. For high speed lines, there
should be a ground trace immediately alongside the signal
lines. For lower speed lines, you may be able to help by placing
a power/ground decap immediately at the signal lines.
Branches and Stubs. This is where a signal leaves the chip,
goes for some distance, then divides into two paths –
a branch too short to be a significant transmission line length
is often called a stub, and looks like a capacitive load.
Avoid both conditions if at all possible. Short stubs may
be allowable for the slower speeds but are not permissible
at higher frequencies. Branches may be tolerated only if placed
immediately at the driver, and then only if the driver can
handle two loads.
It is true that one can modulate the trace width to compensate
for the impedance mismatch (say, one 50 ohm line driving two
100 ohm lines), but that is a last resort, and is sure to
give the PCB layout person heartburn.
Proximity to other traces. This can be a problem if adjacent
traces are spaced quite close (closer than three times the
height above the reference plane). Another case is if there
are two signal layers sandwiched between reference planes.
To minimize these problems, space adjacent traces at least
three times the height above the reference plane to minimize
crosstalk, and space signal traces close to the reference
plane to minimize coupling to signals on other layers.
Corners. This has long been flagged as a problem, but in practice,
it is perhaps the lesser problem of those listed. A square
corner may have a half pF of additional capacitance, not enough
to cause a significant problem. But you can reduce the problem
by running two 45 degree corners or by chamfering the one
corner.
Non-Resistive Loads. The ideal termination is a pure resistance,
but the actual termination will be a resistor shunted by some
capacitance (including gate input plus a possible stub length)
and in series with some inductance (in series with the gate
input, as a minimum). Actual SMT resistors, as mounted, are
not very good above about 500MHz.
Connector Impedance. If you are running twisted pair or coax,
you have some chance at impedance control, at least until
you get to the connector. If you are running a ribbon cable,
you had better figure on having a ground trace alongside your
signal line, preferably one on each side of the signal –
this will get you reasonably close to 50 ohms. Whichever way
you handle the cable, you still need to maintain impedance
control through the connector, again by bracketing the signal
lines with ground lines.
Summary
The message here is short but not necessarily sweet. High
speeds are requiring impedance control for even very short
runs. You need to control the entire path, especially including
the return path. Look beyond the text book for solutions for
the solution. And note that the solution will not be easy
– some necessary technology has not yet been developed.
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